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» Resilient design in scaled CMOS for energy efficiency
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LCTRTS
2004
Springer
14 years 29 days ago
Dynamic voltage scaling for real-time multi-task scheduling using buffers
This paper proposes energy efficient real-time multi-task scheduling (EDF and RM) algorithms by using buffers. The buffering technique overcomes a drawback of previous approaches ...
Chaeseok Im, Soonhoi Ha
GLOBECOM
2010
IEEE
13 years 5 months ago
GreenCloud: A Packet-Level Simulator of Energy-Aware Cloud Computing Data Centers
Cloud computing data centers are becoming increasingly popular for the provisioning of computing resources. The cost and operating expenses of data centers have skyrocketed with th...
Dzmitry Kliazovich, Pascal Bouvry, Yury Audzevich,...
ASPDAC
2004
ACM
118views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Fast and efficient voltage scheduling by evolutionary slack distribution
- To minimize energy consumption by voltage scaling in design of heterogeneousreal-time embeddedsystems, it is necessary to perfom two distinct tasks: task scheduling (TS) and volt...
Bita Gorjiara, Pai H. Chou, Nader Bagherzadeh, Meh...
ISPD
1999
ACM
89views Hardware» more  ISPD 1999»
13 years 12 months ago
VIA design rule consideration in multi-layer maze routing algorithms
—Maze routing algorithms are widely used for finding an optimal path in detailed routing for very large scale integration, printed circuit board and multichip modules In this pap...
Jason Cong, Jie Fang, Kei-Yong Khoo
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
14 years 1 months ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...