133 search results - page 4 / 27 » Resilient design in scaled CMOS for energy efficiency |
CASES
2011
ACM
12 years 7 months ago
2011
ACM
Escalating variations in modern CMOS designs have become a threat to Moore’s law. While previous works have proposed techniques for tolerating variations by trading reliability ...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Power gating has been widely used to reduce subthreshold leakage. However, its efficiency degrades very fast with technology scaling due to the gate leakage of circuits specific t...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
—To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nanoelect...
CASES
2008
ACM
13 years 9 months ago
2008
ACM
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leadin...