133 search results - page 8 / 27 » Resilient design in scaled CMOS for energy efficiency |
SAC
2010
ACM
13 years 7 months ago
2010
ACM
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
ISLPED
2004
ACM
14 years 1 months ago
2004
ACM
As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by dee...
DAC
2008
ACM
13 years 9 months ago
2008
ACM
Graphene nanoribbon FETs (GNRFETs) are promising devices for beyond-CMOS nanoelectronics because of their excellent carrier transport properties and potential for large scale proc...
ISLPED
2000
ACM
13 years 12 months ago
2000
ACM
Recovering and reusing circuit energies that would otherwise be dissipated as heat can reduce the power dissipated by a VLSI chip. To accomplish this requires a power source that ...
ISLPED
2009
ACM
14 years 8 days ago
2009
ACM
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...