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» Resistive Bridging Fault Simulation of Industrial Circuits
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CHES
2004
Springer
121views Cryptology» more  CHES 2004»
14 years 1 months ago
Improving the Security of Dual-Rail Circuits
Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of process...
Danil Sokolov, Julian Murphy, Alexandre V. Bystrov...
VTS
2007
IEEE
100views Hardware» more  VTS 2007»
14 years 2 months ago
Using Scan-Dump Values to Improve Functional-Diagnosis Methodology
In this paper, we identify two main bottlenecks in the functional diagnosis flow and propose new ways to overcome these. Our approach completely eliminates the “Primary Input (P...
Vishnu C. Vimjam, Enamul Amyeen, Ruifeng Guo, Srik...
ETS
2010
IEEE
153views Hardware» more  ETS 2010»
13 years 7 months ago
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes
ÑIn this paper, we present a comparative study on the effects of resistive-bridging defects in the SRAM core-cells, considering different technology nodes. In particular, we analy...
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio,...
ATS
2009
IEEE
111views Hardware» more  ATS 2009»
14 years 3 months ago
Dynamic Compaction in SAT-Based ATPG
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...
Alejandro Czutro, Ilia Polian, Piet Engelke, Sudha...
VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 9 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...