46 search results - page 6 / 10 » Resistive bridge fault modeling, simulation and test generat... |
ITC
2003
IEEE
13 years 12 months ago
2003
IEEE
For ratio-Iddq testing, the test performance is significantly affected by the correlation between two currents of different input patterns as process parameters vary. In this p...
VTS
2002
IEEE
13 years 11 months ago
2002
IEEE
In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and par...
EURODAC
1995
IEEE
13 years 10 months ago
1995
IEEE
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
ICCD
2004
IEEE
14 years 3 months ago
2004
IEEE
— We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanot...
ASPDAC
2004
ACM
14 years 4 days ago
2004
ACM
— This paper presents a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensit...