46 search results - page 8 / 10 » Resistive bridge fault modeling, simulation and test generat... |
ASYNC
2000
IEEE
13 years 11 months ago
2000
IEEE
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
GLVLSI
2009
IEEE
13 years 4 months ago
2009
IEEE
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
VLSID
2005
IEEE
14 years 7 days ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
ATS
2010
IEEE
13 years 4 months ago
2010
IEEE
Abstract--To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...