−In this paper, a novel architecture of a fractional-N phase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequ...
We add specifications of location-aware measurements to performance models in a compositional fashion, promoting precision in performance measurement design. Using immediate actio...
Ashok Argent-Katwala, Jeremy T. Bradley, Allan Cla...
Abstract. We propose three routing strategies for the routing and wavelength assignment (RWA) of scheduled and random lightpath demands in a wavelength-switching mesh network witho...
In this work, we present the analysis of a built-in self-test (BIST) scheme for mixed-signal circuits that is intended to provide on-chip stimulus generation and response analysis...
We propose simple, realistic protocols for polling that allow the responder to plausibly repudiate his response, while at the same time allow accurate statistical analysis of poll ...