57 search results - page 4 / 12 » Retiming and clock scheduling for digital circuit optimizati... |
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in [21] that the full ...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
ISCAPDCS
2003
13 years 8 months ago
2003
Many computation-intensive iterative or recursive applications commonly found in digital signal processing and image processing applications can be represented by data-flow graph...
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
CCECE
2009
IEEE
14 years 4 days ago
2009
IEEE
A truly monolithic clock and data recovery (CDR) circuit for low cost low-end data communication systems has been realized in 0.6ȝm CMOS. The implemented CDR comprises a phase-an...