60 search results - page 9 / 12 » Retiming with Interconnect and Gate Delay |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencie...
TVLSI
1998
13 years 7 months ago
1998
— Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
— The inductance and coupling effects in interconnects and non-linear receiver loads has resulted in complex input signals and output loads for gates in the modern deep submicron...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...