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» Reversible Fault-Tolerant Logic
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DAC
2003
ACM
13 years 12 months ago
Efficient compression and application of deterministic patterns in a logic BIST architecture
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
Peter Wohl, John A. Waicukauski, Sanjay Patel, Min...
DAC
2006
ACM
14 years 7 months ago
Shielding against design flaws with field repairable control logic
Correctness is a paramount attribute of any microprocessor design; however, without novel technologies to tame the increasing complexity of design verification, the amount of bugs...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
VLSID
2006
IEEE
145views VLSI» more  VLSID 2006»
14 years 22 days ago
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Sriniva...
GLVLSI
2010
IEEE
209views VLSI» more  GLVLSI 2010»
13 years 11 months ago
Enhancing debugging of multiple missing control errors in reversible logic
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...
Jean Christoph Jung, Stefan Frehse, Robert Wille, ...
ASPDAC
2005
ACM
97views Hardware» more  ASPDAC 2005»
13 years 8 months ago
Fast synthesis of exact minimal reversible circuits using group theory
- We present fast algorithms to synthesize exact minimal reversible circuits for various types of gates and costs. By reducing reversible logic synthesis problems to group theory p...
Guowu Yang, Xiaoyu Song, William N. N. Hung, Marek...