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VLSI
2005
Springer
14 years 25 days ago
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
1 The increasing test data volume required to ensure high test quality when testing a System-on-Chip is becoming a problem since it (the test data volume) must fit the ATE (Automa...
Erik Larsson, Stina Edbom
DATE
2003
IEEE
96views Hardware» more  DATE 2003»
14 years 19 days ago
Time Domain Multiplexed TAM: Implementation and Comparison
One of the difficult problems which core-based systemon-chip (SoC) designs face is test access. For testing the cores in a SoC, a special mechanism is required, since they are no...
Zahra Sadat Ebadi, André Ivanov
ICCAD
1999
IEEE
148views Hardware» more  ICCAD 1999»
13 years 11 months ago
SAT based ATPG using fast justification and propagation in the implication graph
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
Paul Tafertshofer, Andreas Ganz
KBSE
2006
IEEE
14 years 1 months ago
Detecting Precedence-Related Advice Interference
Aspect-Oriented Programming (AOP) has been proposed in literature to overcome modularization shortcomings such as the tyranny of the dominant decomposition. However, the new langu...
Maximilian Storzer, Florian Forster
HEURISTICS
2000
127views more  HEURISTICS 2000»
13 years 7 months ago
Fast, Efficient Equipment Placement Heuristics for Broadband Switched or Internet Router Networks
Planning and designing the next generation of IP router or switched broadband networks seems a daunting challenge considering the many complex, interacting factors affecting the p...
Joel W. Gannett