167 search results - page 18 / 34 » Robust Techniques for Watermarking Sequential Circuit Design... |
GLVLSI
2003
IEEE
14 years 24 days ago
2003
IEEE
We introduce a simple hierarchical design technique for using dynamic domino circuits to build high-performance self-timed data path circuits. We wrap the dynamic domino circuit i...
DAC
2006
ACM
14 years 1 months ago
2006
ACM
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Side channel attacks are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of triple rail logic agains...
CCS
2003
ACM
14 years 22 days ago
2003
ACM
Network based intruders seldom attack directly from their own hosts, but rather stage their attacks through intermediate “stepping stones” to conceal their identity and origin...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
Partitioning and clustering are crucial steps in circuit layout for handling large scale designs enabled by the deep submicron technologies. Retiming is an important sequential lo...