We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort...
Yu Ben, Laurent El Ghaoui, Kameshwar Poolla, Costa...
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...