15 search results - page 2 / 3 » Robust gate sizing by geometric programming |
ICCD
2004
IEEE
14 years 3 months ago
2004
IEEE
— In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nan...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shif...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
-- Analog circuit sizing under process/parameter variations is formulated as a mini-max geometric programming problem. To tackle such problem, we present a new method that combines...
TVLSI
2008
13 years 6 months ago
2008
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
ASPDAC
2008
ACM
13 years 8 months ago
2008
ACM
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...