15 search results - page 3 / 3 » Robust gate sizing by geometric programming |
VTS
2006
IEEE
14 years 27 days ago
2006
IEEE
Abstract: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU...
GLVLSI
2006
IEEE
14 years 29 days ago
2006
IEEE
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
STOC
1997
ACM
13 years 11 months ago
1997
ACM
Shor has showed how to perform fault tolerant quantum computation when the probability for an error in a qubit or a gate, η, decays with the size of the computation polylogarithmi...
ICCAD
2004
IEEE
14 years 3 months ago
2004
IEEE
In this paper we propose a RObust Analog Design tool (ROAD) for post-tuning analog/RF circuits. Starting from an initial design derived from hand analysis or analog circuit synthe...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...