768 search results - page 125 / 154 » Robustness of Sequential Circuits |
ITC
2003
IEEE
14 years 1 months ago
2003
IEEE
–This paper provides proof of concept for the newly-approved 1149.6 standard by investigating the first silicon implementation of the test receiver. EXTEST and EXTEST_PULSE tests...
ISQED
2000
IEEE
14 years 1 months ago
2000
IEEE
We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and co...
ITC
2000
IEEE
14 years 1 months ago
2000
IEEE
An area efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstructi...
ARVLSI
1999
IEEE
14 years 29 days ago
1999
IEEE
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
ASYNC
1998
IEEE
14 years 27 days ago
1998
IEEE
Analogue to digital (A-D) converters with a xed conversion time are subject to errors due to metastability. These errors will occur in all converter designs with a bounded time fo...