The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
We propose an algorithm for area optimisation of sequential circuits through redundancy removal. The algorithm finds compatible redundancies by implying values over nets in the c...
Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert...
Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power...
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we use...
This paper presents a methodology to transfer self-timed circuit specifications into sequential quantum Boolean circuits (SQBCs) and composable SQBCs (CQBCs). State graphs (SGs) a...