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» Robustness of Sequential Circuits
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DFT
2007
IEEE
104views VLSI» more  DFT 2007»
14 years 1 months ago
Reduction of Fault Latency in Sequential Circuits by using Decomposition
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky
ICCAD
1997
IEEE
66views Hardware» more  ICCAD 1997»
13 years 11 months ago
Sequential optimisation without state space exploration
We propose an algorithm for area optimisation of sequential circuits through redundancy removal. The algorithm finds compatible redundancies by implying values over nets in the c...
Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert...
DATE
1999
IEEE
118views Hardware» more  DATE 1999»
13 years 11 months ago
Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits
Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power...
Michael S. Hsiao
ISQED
2007
IEEE
135views Hardware» more  ISQED 2007»
14 years 1 months ago
MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we use...
Natasa Miskov-Zivanov, Diana Marculescu
ICCD
2005
IEEE
128views Hardware» more  ICCD 2005»
14 years 4 months ago
Automatic Synthesis of Composable Sequential Quantum Boolean Circuits
This paper presents a methodology to transfer self-timed circuit specifications into sequential quantum Boolean circuits (SQBCs) and composable SQBCs (CQBCs). State graphs (SGs) a...
Li-Kai Chang, Fu-Chiung Cheng