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IPPS
2007
IEEE
14 years 3 months ago
A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA
This work addresses the problem of information leakage of cryptographic devices, by using the reconfiguration technique allied to an RNS based arithmetic. The information leaked b...
Daniel Mesquita, Benoît Badrignans, Lionel T...
ITC
2003
IEEE
108views Hardware» more  ITC 2003»
14 years 2 months ago
Optical and Electrical Testing of Latchup in I/O Interface Circuits
Backside light emission and electrical measurements were used to evaluate the susceptibility to latchup of externally cabled I/O pins for a 0.13 µm technology generation [1,2] te...
Franco Stellari, Peilin Song, Moyra K. McManus, Ro...
DAC
1999
ACM
14 years 1 months ago
Interconnect Analysis: From 3-D Structures to Circuit Models
In this survey paper we describethe combination of: discretized integral formulations, sparsication techniques, and krylov-subspace based model-order reduction that has led to rob...
Mattan Kamon, Nuno Alexandre Marques, Yehia Massou...
DATE
2009
IEEE
163views Hardware» more  DATE 2009»
14 years 3 months ago
Fixed points for multi-cycle path detection
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
Vijay D'Silva, Daniel Kroening
ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
14 years 5 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky