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» Robustness of Sequential Circuits
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NIPS
2000
13 years 10 months ago
Processing of Time Series by Neural Circuits with Biologically Realistic Synaptic Dynamics
Experimental data show that biological synapses behave quite differently from the symbolic synapses in common artificial neural network models. Biological synapses are dynamic, i....
Thomas Natschläger, Wolfgang Maass, Eduardo D...
ICCD
2001
IEEE
121views Hardware» more  ICCD 2001»
14 years 5 months ago
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
Noureddine Chabini, El Mostapha Aboulhamid, Yvon S...
ICCAD
2010
IEEE
125views Hardware» more  ICCAD 2010»
13 years 6 months ago
Peak current reduction by simultaneous state replication and re-encoding
Reducing circuit's peak current plays an important role in circuit reliability in deep sub-micron era. For sequential circuits, it is observed that the peak current has a str...
Junjun Gu, Gang Qu, Lin Yuan, Qiang Zhou
ICCAD
1998
IEEE
81views Hardware» more  ICCAD 1998»
14 years 1 months ago
A simultaneous routing tree construction and fanout optimization algorithm
- This paper presents an optimal algorithm for solving the problem of simultaneous fanout optimization and routing tree construction for an ordered set of critical sinks. The algor...
Amir H. Salek, Jinan Lou, Massoud Pedram
FPGA
1998
ACM
160views FPGA» more  FPGA 1998»
14 years 29 days ago
A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs
In this paper, we present a new retiming-based technology mapping algorithm for look-up table-based eld programmable gate arrays. The algorithm is based on a novel iterative proce...
Peichen Pan, Chih-Chang Lin