116 search results - page 8 / 24 » Route Packets, Not Wires: On-Chip Interconnection Networks |
ICPP
1998
IEEE
14 years 26 days ago
1998
IEEE
In this paper, we study fault-tolerantmulticastingin multistage interconnection networks (MINs) for constructing large-scale multicomputers. In addition to point-to-point routing ...
JSS
2006
13 years 8 months ago
2006
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
FPGA
2003
ACM
14 years 1 months ago
2003
ACM
How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the thirddi...
IPPS
2003
IEEE
14 years 1 months ago
2003
IEEE
This work presents a new switching mechanism to tolerate arbitrary faults in interconnection networks with a negligible implementation cost. Although our routing technique can be ...
MICRO
2007
IEEE
14 years 2 months ago
2007
IEEE
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...