In this paper, we study fault-tolerantmulticastingin multistage interconnection networks (MINs) for constructing large-scale multicomputers. In addition to point-to-point routing ...
Jinsoo Kim, Jaehyung Park, Jung Wan Cho, Hyunsoo Y...
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the thirddi...
This work presents a new switching mechanism to tolerate arbitrary faults in interconnection networks with a negligible implementation cost. Although our routing technique can be ...
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...