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» Routers with Very Small Buffers
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VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 10 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
IPPS
1998
IEEE
14 years 2 months ago
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
Switch-based interconnects are used in a number of application domains including parallel system interconnects, local area networks, and wide area networks. However, very few swit...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
TASE
2011
IEEE
13 years 4 months ago
Multiclass Flow Line Models of Semiconductor Manufacturing Equipment for Fab-Level Simulation
—For multiclass flow line models, we identify a class of service times that allow a decomposition of the system into subsets of servers called channels. In each channel, the cus...
James R. Morrison
ICCD
2003
IEEE
129views Hardware» more  ICCD 2003»
14 years 6 months ago
Reducing dTLB Energy Through Dynamic Resizing
Translation Look-aside Buffer (TLB), which is small Content Addressable Memory (CAM) structure used to translate virtual addresses to physical addresses, can consume significant ...
Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubr...
CN
2007
98views more  CN 2007»
13 years 9 months ago
Analysis of point-to-point packet delay in an operational network
— In this paper we perform a detailed analysis of point-to-point packet delay in an operational tier-1 network. The point-to-point delay is the time between a packet entering a r...
Baek-Young Choi, Sue B. Moon, Zhi-Li Zhang, Konsta...