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» Routing in Modular Fault Tolerant Multiprocessor Systems
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ASPLOS
2010
ACM
14 years 2 months ago
Power routing: dynamic power provisioning in the data center
Data center power infrastructure incurs massive capital costs, which typically exceed energy costs over the life of the facility. To squeeze maximum value from the infrastructure,...
Steven Pelley, David Meisner, Pooya Zandevakili, T...
HPCA
2006
IEEE
14 years 8 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
DAC
2011
ACM
12 years 7 months ago
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
Andrew DeOrio, Konstantinos Aisopos, Valeria Berta...
NGC
2000
Springer
13 years 11 months ago
The use of hop-limits to provide survivable ATM group communications
We examine the use of a hop-limit constraint with techniques to provide survivability for connection-oriented ATM group communications. A hop-limit constraint is an approach that ...
William Yurcik, David Tipper, Deep Medhi
MICRO
2008
IEEE
119views Hardware» more  MICRO 2008»
14 years 2 months ago
The StageNet fabric for constructing resilient multicore systems
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leadin...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...