55 search results - page 6 / 11 » Run-time compaction of FPGA designs |
FPGA
2007
ACM
14 years 4 months ago
2007
ACM
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
ICCD
2007
IEEE
14 years 6 months ago
2007
IEEE
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
DAC
2008
ACM
14 years 10 months ago
2008
ACM
We are presenting a new concept of an application-specific processor that is capable of transmuting its instruction set according to non-predictive application behavior during run...
CHES
2007
Springer
14 years 4 months ago
2007
Springer
This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation arch...
FPL
2004
Springer
14 years 3 months ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...