55 search results - page 8 / 11 » Run-time compaction of FPGA designs |
FPGA
2004
ACM
13 years 11 months ago
2004
ACM
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
ACSD
2006
IEEE
14 years 1 months ago
2006
IEEE
An optimized functional design space exploration method for multimedia applications is proposed. The basis of the method is a way of representing the dependency and the concurrenc...
ASAP
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper we present a novel adder/subtracter arithmetic unit that combines Binary and Binary Code Decimal (BCD) operations. The proposed unit uses effective addition/subtract...
CDES
2006
13 years 8 months ago
2006
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
ARC
2008
Springer
13 years 9 months ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....