61 search results - page 11 / 13 » SAMBA-Bus: A High Performance Bus Architecture for System-on... |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
IPPS
2000
IEEE
14 years 9 days ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
DAS
2008
Springer
13 years 9 months ago
2008
Springer
In classification tasks, class-modular strategy has been widely used. It has outperformed classical strategy for pattern classification task in many applications [1]. However, in ...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
Abstract— High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data lay...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the domi...