261 search results - page 5 / 53 » SAT-Based Algorithms for Logic Minimization |
CSREAESA
2004
13 years 8 months ago
2004
: In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal opt...
GLVLSI
2003
IEEE
14 years 9 days ago
2003
IEEE
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
ECCC
2007
13 years 7 months ago
2007
Satisfiability algorithms have become one of the most practical and successful approaches for solving a variety of real-world problems, including hardware verification, experime...
IAT
2009
IEEE
14 years 1 months ago
2009
IEEE
Abstract—In semantic matchmaking processes it is often useful, when the obtained match is not full, to provide explanations for the mismatch, to leverage further interaction and/...
ICCAD
2004
IEEE
14 years 3 months ago
2004
IEEE
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...