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» SOC Test Scheduling Using Simulated Annealing
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CODES
2005
IEEE
14 years 1 months ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
PCI
2005
Springer
14 years 29 days ago
TSIC: Thermal Scheduling Simulator for Chip Multiprocessors
Abstract. Increased power density, hot-spots, and temperature gradients are severe limiting factors for today’s state-of-the-art microprocessors. However, the flexibility offer...
Kyriakos Stavrou, Pedro Trancoso
GECCO
2005
Springer
113views Optimization» more  GECCO 2005»
14 years 1 months ago
Search-based mutation testing for Simulink models
The efficient and effective generation of test-data from high-level models is of crucial importance in advanced modern software engineering. Empirical studies have shown that muta...
Yuan Zhan, John A. Clark
IJHIS
2007
89views more  IJHIS 2007»
13 years 7 months ago
A new hybrid heuristic for driver scheduling
This paper describes a new hybrid method based on the application of the Population Training Algorithm (PTA) and linear programming (LP) for generation of schedules for drivers in...
Geraldo R. Mauri, Luiz Antonio Nogueira Lorena
DAC
1994
ACM
13 years 11 months ago
Synthesis of Instruction Sets for Pipelined Microprocessors
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
Ing-Jer Huang, Alvin M. Despain