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» SOC Test Scheduling Using Simulated Annealing
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DATE
2006
IEEE
134views Hardware» more  DATE 2006»
14 years 1 months ago
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
1 This paper presents a test scheduling approach for system-onchip production tests with peak-power constraints. An abort-onfirst-fail test approach is assumed, whereby the test is...
Zhiyuan He, Zebo Peng, Petru Eles
TCAD
2002
73views more  TCAD 2002»
13 years 7 months ago
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints
Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource c...
Vikram Iyengar, Krishnendu Chakrabarty
IPPS
1998
IEEE
13 years 11 months ago
Meta-heuristics for Circuit Partitioning in Parallel Test Generation
In this communication Simulated Annealing and Genetic Algorithms, are applied to the graph partitioning problem. These techniques mimic processes in statistical mechanics and biol...
Consolación Gil, Julio Ortega, Antonio F. D...
HICSS
2005
IEEE
110views Biometrics» more  HICSS 2005»
14 years 1 months ago
A Trust-based Negotiation Mechanism for Decentralized Economic Scheduling
Abstract— This paper presents a decentralized negotiation protocol for cooperative economic scheduling in a supply chain environment. For this purpose we designed autonomous agen...
Tim Stockheim, Oliver Wendt, Michael Schwind
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
14 years 1 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...