Sciweavers

97 search results - page 5 / 20
» SRAM Cell Current in Low Leakage Design
Sort
View
ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
14 years 2 months ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
DAC
2002
ACM
14 years 8 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
CF
2011
ACM
12 years 7 months ago
Hybrid high-performance low-power and ultra-low energy reliable caches
Ubiquitous computing has become a very popular paradigm. The most suitable technological solution for those systems consists of using hybrid processors able to operate at high vol...
Bojan Maric, Jaume Abella, Francisco J. Cazorla, M...
ISQED
2009
IEEE
196views Hardware» more  ISQED 2009»
14 years 2 months ago
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is redu...
Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto...
ISLPED
2004
ACM
157views Hardware» more  ISLPED 2004»
14 years 1 months ago
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors
We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips. The innovative idea is the use of 4T SRAM cell...
Stefanos Kaxiras, Polychronis Xekalakis