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» SRAM Cell Current in Low Leakage Design
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ICCAD
2004
IEEE
85views Hardware» more  ICCAD 2004»
14 years 4 months ago
Improving soft-error tolerance of FPGA configuration bits
Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it...
Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykr...
MICRO
2002
IEEE
128views Hardware» more  MICRO 2002»
14 years 18 days ago
Compiler-directed instruction cache leakage optimization
Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consum...
Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut...
CAL
2002
13 years 7 months ago
Implementing Decay Techniques using 4T Quasi-Static Memory Cells
Abstract-This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While ...
Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin...
JCP
2008
232views more  JCP 2008»
13 years 7 months ago
Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation
Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper...
Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira ...
ICCD
2008
IEEE
148views Hardware» more  ICCD 2008»
14 years 2 months ago
Adaptive SRAM memory for low power and high yield
— SRAMs typically represent half of the area and more than half of the transistors on a chip today. Variability increases as feature size decreases, and the impact of variability...
Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jaco...