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» Satisfiability-Based Detailed FPGA Routing
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FPGA
1999
ACM
155views FPGA» more  FPGA 1999»
13 years 11 months ago
FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density
In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distribution of routing segment lengths and the best mix of pass transist...
Vaughn Betz, Jonathan Rose
FPGA
2006
ACM
125views FPGA» more  FPGA 2006»
13 years 11 months ago
Armada: timing-driven pipeline-aware routing for FPGAs
While previous research has shown that FPGAs can efficiently implement many types of computations, their flexibility inherently limits their clock rate. Several research groups ha...
Kenneth Eguro, Scott Hauck
ICCAD
2003
IEEE
194views Hardware» more  ICCAD 2003»
14 years 4 months ago
On the Interaction Between Power-Aware FPGA CAD Algorithms
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
Julien Lamoureux, Steven J. E. Wilton
MSE
2003
IEEE
101views Hardware» more  MSE 2003»
14 years 19 days ago
Internet-based Tool for System-On-Chip Project Testing and Grading
A tool has been developed to automate the testing and grading of design projects implemented in reprogrammable hardware. The server allows multiple students to test circuits in FP...
Christopher K. Zuver, Christopher E. Neely, John W...
DAC
1993
ACM
13 years 11 months ago
A Negative Reinforcement Method for PGA Routing
We present an efficient and effective method for the detailed routing of symmetrical or sea-of-gates FPGA architectures. Instead of breaking the problem into 2-terminal net collec...
Forbes D. Lewis, Wang Chia-Chi Pong