212 search results - page 29 / 43 » Scalable Hardware Architecture for Real-Time Dynamic Program... |
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
With the right techniques, multicore architectures may be able to continue the exponential performance trend that elevated the performance of applications of all types for decades...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
HPCA
2008
IEEE
14 years 7 months ago
2008
IEEE
Dynamic binary translation (DBT) is a runtime instrumentation technique commonly used to support profiling, optimization, secure execution, and bug detection tools for application...
VLSISP
2008
13 years 7 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...