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» Scalable Memory Hierarchies for Embedded Manycore Systems
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DATE
1999
IEEE
113views Hardware» more  DATE 1999»
13 years 11 months ago
Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
William Fornaciari, Donatella Sciuto, Cristina Sil...
IPPS
2007
IEEE
14 years 1 months ago
Scalable, Distributed, Dynamic Resource Management for the ARMS Distributed Real-Time Embedded System
We present a scalable, hierarchical control system for the dynamic resource management of a distributed real-time embedded (DRE) system. This DRE is inspired by the DARPA Adaptive...
Kurt Rohloff, Yarom Gabay, Jianming Ye, Richard E....
DATE
2006
IEEE
159views Hardware» more  DATE 2006»
14 years 1 months ago
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...
MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
14 years 1 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
CSE
2012
IEEE
12 years 3 months ago
Accelerating Quantum Monte Carlo Simulations of Real Materials on GPU Clusters
—Continuum quantum Monte Carlo (QMC) has proved to be an invaluable tool for predicting the properties of matter from fundamental principles. By solving the manybody Schr¨odinge...
Kenneth Esler, Jeongnim Kim, David M. Ceperley, Lu...