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» Scale in Chip Interconnect requires Network Technology
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DAC
2003
ACM
14 years 8 months ago
A survey of techniques for energy efficient on-chip communication
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
Vijay Raghunathan, Mani B. Srivastava, Rajesh K. G...
ISCA
2008
IEEE
130views Hardware» more  ISCA 2008»
14 years 1 months ago
Corona: System Implications of Emerging Nanophotonic Technology
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance...
Dana Vantrease, Robert Schreiber, Matteo Monchiero...
LCN
2005
IEEE
14 years 1 months ago
A New Scheme for Interconnecting LANs with Label Switching Bridges
Ethernet, which has traditionally been the dominant technology in Local Area Networks, is now facing new challenges due to the fact that networks have scaled and today’s applica...
Thierry K. Feuzeu, Bernard Cousin
ICCAD
2002
IEEE
73views Hardware» more  ICCAD 2002»
14 years 4 months ago
Shaping interconnect for uniform current density
As the VLSI technology scaling down, the electromigration problem becomes one of the major concerns in high-performance IC design for both power network and signal interconnects. ...
Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, ...
NOCS
2008
IEEE
14 years 1 months ago
Reducing the Interconnection Network Cost of Chip Multiprocessors
This paper introduces a cost-effective technique to deal with CMP coherence protocol requirements from the interconnection network point of view. A mechanism is presented to avoid...
Pablo Abad, Valentin Puente, José-Án...