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» Scaling and Packing on a Chip Multiprocessor
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MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
14 years 1 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
ISCA
2000
IEEE
90views Hardware» more  ISCA 2000»
13 years 12 months ago
A scalable approach to thread-level speculation
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
SAC
2009
ACM
14 years 2 months ago
GTfold: a scalable multicore code for RNA secondary structure prediction
The prediction of the correct secondary structures of large RNAs is one of the unsolved challenges of computational molecular biology. Among the major obstacles is the fact that a...
Amrita Mathuriya, David A. Bader, Christine E. Hei...
ICCD
2007
IEEE
215views Hardware» more  ICCD 2007»
14 years 4 months ago
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li...
ICCAD
2007
IEEE
91views Hardware» more  ICCAD 2007»
14 years 4 months ago
Variation-aware task allocation and scheduling for MPSoC
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. As a result, a paradigm shift from determ...
Feng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia W...