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» Scaling and Packing on a Chip Multiprocessor
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ISCA
2009
IEEE
178views Hardware» more  ISCA 2009»
14 years 2 months ago
Thread motion: fine-grained power management for multi-core systems
Dynamic voltage and frequency scaling (DVFS) is a commonly-used powermanagement scheme that dynamically adjusts power and performance to the time-varying needs of running programs...
Krishna K. Rangan, Gu-Yeon Wei, David Brooks
ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
14 years 2 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li
ISCAS
2006
IEEE
87views Hardware» more  ISCAS 2006»
14 years 1 months ago
NoC monitoring: impact on the design flow
Abstract— Networks-on-chip (NoCs) are a scalable interconnect solution to large scale multiprocessor systems on chip and are rapidly becoming reality. As the ratio of embedded co...
Calin Ciordas, Kees Goossens, Andrei Radulescu, Tw...
ISQED
2006
IEEE
101views Hardware» more  ISQED 2006»
14 years 1 months ago
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Oz...
ICS
2010
Tsinghua U.
13 years 6 months ago
An approach to resource-aware co-scheduling for CMPs
We develop real-time scheduling techniques for improving performance and energy for multiprogrammed workloads that scale nonuniformly with increasing thread counts. Multithreaded ...
Major Bhadauria, Sally A. McKee