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» Scaling and Packing on a Chip Multiprocessor
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ISLPED
2005
ACM
123views Hardware» more  ISLPED 2005»
14 years 1 months ago
Coordinated, distributed, formal energy management of chip multiprocessors
Designers are moving toward chip-multiprocessors (CMPs) to leverage application parallelism for higher performance while keeping design complexity under control. However, to date,...
Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Mar...
ASPDAC
2007
ACM
174views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS Systems
Dynamic voltage scaling (DVS) circuits have been widely adopted in many computing systems to provide tradeoff between performance and power consumption. The effective use of energ...
Jian-Jia Chen, Chuan-Yue Yang, Tei-Wei Kuo, Chi-Sh...
DATE
2007
IEEE
105views Hardware» more  DATE 2007»
14 years 1 months ago
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
— Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of po...
Meeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, ...
LCTRTS
2010
Springer
13 years 5 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
IEEEPACT
2008
IEEE
14 years 1 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang