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ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
14 years 4 months ago
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses
— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression sche...
Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Maha...
ICCAD
2005
IEEE
117views Hardware» more  ICCAD 2005»
14 years 4 months ago
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
Abstract— We present in this paper a new interconnect-driven multilevel floorplanning, called IMF, to handle large-scale building-module designs. Unlike the traditional multilev...
Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin
SOSP
2005
ACM
14 years 4 months ago
THINC: a virtual display architecture for thin-client computing
Rapid improvements in network bandwidth, cost, and ubiquity combined with the security hazards and high total cost of ownership of personal computers have created a growing market...
Ricardo A. Baratto, Leonard N. Kim, Jason Nieh
VEE
2010
ACM
327views Virtualization» more  VEE 2010»
14 years 2 months ago
AASH: an asymmetry-aware scheduler for hypervisors
Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs...
Vahid Kazempour, Ali Kamali, Alexandra Fedorova
CVPR
2009
IEEE
14 years 2 months ago
Tubular anisotropy for 2D vessel segmentation
In this paper, we present a new approach for segmentation of tubular structures in 2D images providing minimal interaction. The main objective is to extract centerlines and bounda...
Fethallah Benmansour, Laurent D. Cohen, Max W. K. ...