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» Scan chain clustering for test power reduction
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TC
2008
13 years 7 months ago
Low-Transition Test Pattern Generation for BIST-Based Applications
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...
Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed
ICCD
2007
IEEE
161views Hardware» more  ICCD 2007»
14 years 4 months ago
Scan chain design for three-dimensional integrated circuits (3D ICs)
Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed...
Xiaoxia Wu, Paul Falkenstern, Yuan Xie
TODAES
2011
107views more  TODAES 2011»
13 years 2 months ago
Scan-based attacks on linear feedback shift register based stream ciphers
—In this paper, we present an attack on stream cipher implementations by determining the scan chain structure of the linear feedback shift registers in their implementations. Alt...
Yu Liu, Kaijie Wu, Ramesh Karri
ICCD
2006
IEEE
84views Hardware» more  ICCD 2006»
14 years 4 months ago
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation
—X-filling is preferred for low-capture-power scan test generation, since it reduces IR-drop-induced yield loss without the need of any circuit modification. However, the effecti...
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Y...
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
13 years 11 months ago
RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power
As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed. Extended frequ...
Hao Fang, Chenguang Tong, Xu Cheng