1263 search results - page 238 / 253 » Scatter-Add in Data Parallel Architectures |
HPCA
2002
IEEE
14 years 8 months ago
2002
IEEE
We propose a low overhead, on-line memory monitoring scheme utilizing a set of novel hardware counters. The counters act like pressure gauges indicating the marginal gain in the n...
ISPASS
2007
IEEE
14 years 2 months ago
2007
IEEE
Address re-mapping techniques in so-called active memory systems have been shown to dramatically increase the performance of applications with poor cache and/or communication beha...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, we present hthreads, a unifying programming model for specifying application threads running within a hybrid CPU/FPGA system. Threads are specified from a single p...
IWCMC
2006
ACM
14 years 1 months ago
2006
ACM
In this paper we present and evaluate a new technique to lower packet-level error rates of application layer connections in wireless ad-hoc networks. In our scheme, data packets s...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...