174 search results - page 8 / 35 » Schedule-aware performance estimation of communication archi... |
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
CODES
2006
IEEE
14 years 2 months ago
2006
IEEE
Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate suc...
CODES
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
Rapid evaluation and design space exploration at the algorithmic level are important issues in the design cycle. In this paper we propose an original area vs delay estimation meth...