125 search results - page 21 / 25 » Scheduling to minimize power consumption using submodular fu... |
FCCM
2000
IEEE
14 years 29 days ago
2000
IEEE
Simplifying the programming models is paramount to the success of reconfigurable computing. We apply the principles of object-oriented programming to the design of stream archite...
ALGORITHMICA
2011
13 years 5 days ago
2011
Speed scaling is a power management technique that involves dynamically changing the speed of a processor. This gives rise to dual-objective scheduling problems, where the operati...
DAC
1996
ACM
14 years 21 days ago
1996
ACM
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...