An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell compone...
Michael I. Fuller, James P. Mabry, John A. Hossack...
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Ultra-deep submicron manufacturability impacts physical design (PD) through complex layout rules and large guardbands for process variability; this creates new requirements for ne...
The game and entertainment industry plays an enormous role within the development and extensive usage of new technologies. They are one major technology driver concerning the deve...
Carsten Matysczok, Rafael Radkowski, Jan Berssenbr...
This paper reports on the development of a novel mixed reality I/O device tailored to the requirements of interaction with geo-spatial data in the immediate environment of the use...