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GLVLSI
2003
IEEE
173views VLSI» more  GLVLSI 2003»
14 years 20 days ago
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications
An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell compone...
Michael I. Fuller, James P. Mabry, John A. Hossack...
IEEEPACT
2000
IEEE
13 years 11 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier
ICCAD
2003
IEEE
145views Hardware» more  ICCAD 2003»
14 years 4 months ago
Manufacturing-Aware Physical Design
Ultra-deep submicron manufacturability impacts physical design (PD) through complex layout rules and large guardbands for process variability; this creates new requirements for ne...
Puneet Gupta, Andrew B. Kahng
ACMACE
2004
ACM
14 years 25 days ago
AR-bowling: immersive and realistic game play in real environments using augmented reality
The game and entertainment industry plays an enormous role within the development and extensive usage of new technologies. They are one major technology driver concerning the deve...
Carsten Matysczok, Rafael Radkowski, Jan Berssenbr...
SIMVIS
2007
13 years 8 months ago
Development of a Mixed Reality Device for Interactive On-Site Geo-visualization
This paper reports on the development of a novel mixed reality I/O device tailored to the requirements of interaction with geo-spatial data in the immediate environment of the use...
Volker Paelke, Claus Brenner