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» Secure Configuration of Field Programmable Gate Arrays
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DFT
2007
IEEE
152views VLSI» more  DFT 2007»
13 years 11 months ago
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of Sof...
Cristiana Bolchini, Antonio Miele, Marco D. Santam...
FPL
2005
Springer
86views Hardware» more  FPL 2005»
14 years 1 months ago
On the Reliability Evaluation of SRAM-Based FPGA Designs
Benefits of Field Programmable Gate Arrays (FPGAs) have lead to a spectrum of use ranging from consumer products to astronautics. This diversity necessitates the need to evaluate ...
Olivier Héron, Talal Arnaout, Hans-Joachim ...
BIOADIT
2004
Springer
14 years 27 days ago
A Hardware Implementation of a Network of Functional Spiking Neurons with Hebbian Learning
Abstract. In this paper we present a functional model of a spiking neuron intended for hardware implementation. Some features of biological spiking neuabstracted, while preserving ...
Andres Upegui, Carlos Andrés Peña-Re...
FPL
2004
Springer
87views Hardware» more  FPL 2004»
14 years 26 days ago
Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs
This paper presents an innovative way to deploy Bitstream Intellectual Property (BIP) cores. By using standard tools to generate bitstreams for Field Programmable Gate Arrays (FPGA...
Edson L. Horta, John W. Lockwood
IOLTS
2003
IEEE
124views Hardware» more  IOLTS 2003»
14 years 23 days ago
Designing FPGA based Self-Testing Checkers for m-out-of-n Codes
The paper describes a specific method for designing selfchecking checkers for m-out-of-n codes. The method is oriented to the Field Programmable Gate Arrays technology and is base...
A. Matrosova, Vladimir Ostrovsky, Ilya Levin, K. N...