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ICFP
2012
ACM
11 years 11 months ago
Proof-producing synthesis of ML from higher-order logic
The higher-order logic found in proof assistants such as Coq and various HOL systems provides a convenient setting for the development and verification of pure functional program...
Magnus O. Myreen, Scott Owens
GLVLSI
2007
IEEE
167views VLSI» more  GLVLSI 2007»
14 years 3 months ago
A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...
Dariusz Kania
ICCAD
1997
IEEE
142views Hardware» more  ICCAD 1997»
14 years 1 months ago
Library-less synthesis for static CMOS combinational logic circuits
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...
Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullel...
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
14 years 2 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
DATE
2010
IEEE
175views Hardware» more  DATE 2010»
14 years 24 days ago
Approximate logic synthesis for error tolerant applications
─ Error tolerance formally captures the notion that – for a wide variety of applications including audio, video, graphics, and wireless communications – a defective chip that...
Doochul Shin, Sandeep K. Gupta