1210 search results - page 54 / 242 » Secure Logic Synthesis |
DAC
2009
ACM
14 years 11 months ago
2009
ACM
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...
FPGA
2009
ACM
14 years 4 months ago
2009
ACM
We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is cap...
DSD
2010
IEEE
13 years 7 months ago
2010
IEEE
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...
CORR
2010
Springer
13 years 10 months ago
2010
Springer
The signcryption is a relatively new cryptographic technique that is supposed to fulfill the functionalities of encryption and digital signature in a single logical step. Although...
DATE
2010
IEEE
14 years 3 months ago
2010
IEEE
Abstract—We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) sys...