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ICCAD
2002
IEEE
110views Hardware» more  ICCAD 2002»
14 years 4 months ago
Whirlpool PLAs: a regular logic structure and their synthesis
 A regular circuit structure called a Whirlpool PLA (WPLA) is proposed. It is suitable for the implementation of finite state machines as well as combinational logic. A WPLA is ...
Fan Mo, Robert K. Brayton
CHES
2005
Springer
82views Cryptology» more  CHES 2005»
14 years 1 months ago
Masking at Gate Level in the Presence of Glitches
Abstract. It has recently been shown that logic circuits in the implementation of cryptographic algorithms, although protected by “secure” random masking schemes, leak side-cha...
Wieland Fischer, Berndt M. Gammel
ICCD
1994
IEEE
142views Hardware» more  ICCD 1994»
13 years 11 months ago
Grammar-Based Optimization of Synthesis Scenarios
Systems for multi-level logic optimization are usually based on a set of specialized, loosely-related transformations which work on a network representation. The sequence of trans...
Andreas Kuehlmann, Lukas P. P. P. van Ginneken
ATVA
2007
Springer
152views Hardware» more  ATVA 2007»
14 years 1 months ago
Bounded Synthesis
Abstract. The bounded synthesis problem is to construct an implementation that satisfies a given temporal specification and a given bound on the number of states. We present a so...
Sven Schewe, Bernd Finkbeiner
CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...