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IPPS
2002
IEEE
14 years 13 days ago
Overview of Hydra: A Concurrent Language for Synchronous Digital Circuit Design
Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit speci...
John O'Donnell
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
13 years 11 months ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...
NN
2008
Springer
152views Neural Networks» more  NN 2008»
13 years 7 months ago
Compact silicon neuron circuit with spiking and bursting behaviour
A silicon neuron circuit that produces spiking and bursting firing patterns, with biologically plausible spike shape, is presented. The circuit mimics the behaviour of known class...
Jayawan H. B. Wijekoon, Piotr Dudek
ICCAD
1995
IEEE
136views Hardware» more  ICCAD 1995»
13 years 11 months ago
A controller-based design-for-testability technique for controller-data path circuits
This paper investigates the effect of the controller on the testability of sequential circuits composed of controllers and data paths. It is shown that even when both the controll...
Sujit Dey, Vijay Gangaram, Miodrag Potkonjak
DATE
2009
IEEE
90views Hardware» more  DATE 2009»
14 years 2 months ago
A scalable method for the generation of small test sets
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compat...
Santiago Remersaro, Janusz Rajski, Sudhakar M. Red...