Soft error due to ionizing radiation is emerging as a major concern for future technologies. The measurement unit for failures due to soft errors is called Failure-In-Time (FIT) t...
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
Optimized locally exhaustive test pattern generators based on linear sums promise a low overhead, but have an irregular structure. The paper presents a new algorithm able to compu...