376 search results - page 19 / 76 » Self-Assembled Circuit Patterns |
EVOW
1999
Springer
13 years 11 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
ISPD
2006
ACM
14 years 1 months ago
2006
ACM
In this paper, we propose more accurate power/ground network circuit model, which consider both via and ground bounce effects to improve the performance estimation accuracy of on-...
DSD
2010
IEEE
13 years 6 months ago
2010
IEEE
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
Abstract--We present a processor-programmable built-in selftest (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circ...
JOCN
2010
13 years 6 months ago
2010
■ Although many examples exist for shared neural representations of self and other, it is unknown how such shared representations interact with the rest of the brain. Furthermor...